AMD Chasing Intel to 45nm by 2008
In the race to reduce, this could be AMD's window of opportunity. On the opposite end of the scale, IBM is working on a copper-doped compound with a low-k dielectric property, with the intention of reducing capacitance in the trenches or channels in-between the gates. IBM has had the same problem Intel and everyone else has faced: chemical compatibility with the silicon dioxide substrate.
The advancement that made semiconductors possible at this size in the first place was the layering process of silicon germanium (SiGe) atop silicon, which results in a feature naturally called strain. For the atoms to bond, the SiGe compound literally has to stretch, and the resulting strain reduces the distance that electrons have to travel, thus reducing the amount of energy required to implement switching.
At lower lithography levels, however, you need different materials to be able to accomplish similar efficiencies. Imagine if the SiGe layer were a swatch of foam rubber you're using to cover a small cushion. The smaller the swatch, the lesser the elasticity, and before too long, it's not a cushion. At 45 nm levels, compounds tend not to retain their stress levels over time, which means the semiconductor tears itself apart at the seams.
Perhaps no longer, though, as IBM's and AMD's announcement this morning made clear: They've implemented a technique based on the so-called SiCOH ("seek - oh") compound IBM announced last June, whose k-value is lower than 3.0. The property engineers were looking for is called stress memorization (SMT) - a way for the compound to resume its original stress in the midst of a continuous current. This morning, the team says they've found it.
"We show SMT process optimization for the 45nm technology node, and clarify the root cause of the performance gain," says the joint paper, presented at the International Electron Devices Meeting today. "Using [a] mobility extraction technique, along with short channel capacitance analysis, we show that the SMT gain is indeed caused by increased electron mobility and not from improvements in gate activation or FET [transistor] S/D resistance."
In other words, it's the AMD/IBM low-k technique that's responsible for the perceived increase in performance, not anything related to an Intel-like high-K technique.
"In transistor gate dielectrics, high-k is desirable because it gives high performance with low leakage," explained Intel's Aakre. "In interconnects, low-k is desirable as it leads to faster signal transmission times."
AMD's roadmap for 45nm lithography puts conversion at least six months behind Intel's goal. But the low-k problem will still be a problem for Intel, as much as it has been for AMD and IBM (which had more ground to make up than even AMD, only now moving away from 90nm). Solving just this one problem could put AMD back even with Intel in terms of process innovation, in less than two years' time. That is, assuming Intel does nothing in the meantime, which has never been the case.
Speaking of "in the meantime," AMD will have to continue to be a processor company for the masses in the interim, which means it will have to stay competitive in the price/performance area at the same time it's almost a generation behind Intel. In a recent interview with BetaNews, AMD Athlon 64 X2 product manager David Schwartzbach promised that AMD has plans to maintain competitive value against Intel within the coming months, which he believes will entrench his company as the value leader until the 45nm era is finally upon us. More of BetaNews' interview with Schwartzbach and others at AMD in the coming days.
