Intel Officially Confirms Integrated Memory Controller for 45nm Nehalem
This afternoon, Intel confirmed to BetaNews what its executive vice president, Pat Gelsinger, inadvertently revealed in comments to reporters several weeks ago, and what the Wall Street Journal learned this morning after having read The Register from several days ago: Intel's second generation of 45nm CPU architecture, code-named "Nehalem," will integrate memory controllers typically featured in the northbridge component of Intel chipsets, into the CPU itself.
Actually, knowledgeable sources came to the conclusion that Intel must be integrating its memory controller into the CPU based on information received as early as last July. TG Daily carefully glanced over the possibility at that time, before raising speculation the following September: Intel's comments to that time about something it calls scalable cache sizes led to no other conclusion. How could a chipset possibly scale the cache of something residing off the main memory bus?
The publication raised the question directly with Intel again last February. But surprisingly, an Intel spokesperson downplayed the rumors by effectively confirming that Intel would not integrate memory controllers into its Penryn CPUs -- the first generation of 45nm architecture. Intel then went on to explain why such integration may be a bad design choice, using AMD -- which has used integrated HyperTransport since before the dual-core era - as a negative example.
In an amended fact sheet today, Intel states integrated memory controllers will be a Nehalem feature when that new microarchitecture begins production in 2008. It also has added a curious new characterization: "simultaneous multi-threading," which it now states is similar to hyperthreading.
HT technology was introduced in 2005 as a kind of stopgap measure prior to the introduction of dual-core processors - an introduction many believed to have been substantively expedited by AMD. Previously, Intel effectively confirmed to multiple press sources that it would be using HT in Nehalem, though this re-characterization appears to have borrowed the same cloud that once hung over the northbridge, to fuzzify the issue of on-board parallelism.
Never a company to let an opportunity for uncertainty over its rival go to waste, AMD weighed in this afternoon in a comment to BetaNews: "Our competitor's announcement today is further validation that [Intel's] current architecture will not be competitive with Barcelona [AMD's forthcoming 65nm CPUs later this year] until they make this transition that we showed the industry in 2003 with Direct Connect Architecture," remarked AMD corporate VP Randy Allen.
"The dual-core performance leadership we have today is building a bridge to Barcelona and the increased performance it will deliver in a non-disruptive fashion. We are not requiring our customers to make wholesale infrastructure changes in order to achieve incremental performance gains."