Intel to Show Off 1 TFlop, 80-core CPU

At a meeting of the International Solid-State Circuits Conference in Santa Clara later this afternoon (early this evening East coast time), engineers from Intel are slated to demonstrate a working version of a conceptual CPU, using designs the company may integrate into future product lines. As promised during the last Intel Developers' Forum, this concept CPU will incorporate 80 cores using an experimental "network-on-a-chip" architecture, which enables the cores to share data without depositing it in memory first.

Last month, in an about-face in its strategy toward waging the "dual-core duel," AMD CEO Hector Ruiz pronounced, "It's not about the cores," in an attempt to deflect attention toward those parts of CPU architecture where AMD may still hold a slight advantage. Today's ISSCC conference is evidently where Intel responds, "The heck it's not!"

A few new technical details were revealed today in, of all places, the agenda booklet for today's ISSCC. "A 275mm2 network-on-chip architecture contains 80 tiles arranged as a 10*8 2D array of floating-point cores and packet-switched routers, operating at 4GHz," reads the brochure. "The 15-FO4 design employs mesochronous clocking, fine-grained clock gating, dynamic sleep transistors, and body-bias techniques. The 65nm 100M transistor die is designed to achieve a peak performance of 1.0TFLOPS at 1V while dissipating 98W."

If you're a regular ISSCC attendee, you already know what the above means. For the rest of humanity, here's a bit of explanation:

  • Mesochronous clocking refers to the capability of a chip to accompany data with clock synchronization signals, rather than have an independent system clock generate ticks. With processor designs becoming vastly more diverse and segmented, there's a point at which the work required to maintain operations throughout all those compartments at one time becomes futile. One alternative approach is asynchronous clocking, which simply lets each department march to its own drum beat, although the beats are brought together in tandem. The mesochronous approach concedes that as the chambers of the CPU become more diverse and cavernous, you can't make the clock tick "loud" enough to pervade every room at once. So instead, clock signals are inserted into the data stream, and permitted to flow through the system as they will, with the latencies worked through later on.
  • Tiles refers to the multi-core architecture Intel is trying with this concept, in which processor cores are quite literally stamped one adjacent to the other, with the patterns in one running flush with those in the other, like laying linoleum tile. Here, tiles are laid in a 10 x 8 block, with each tile containing a core and a router. The latter is used for distributing packets within the chip itself, managing its own "micro-internet."
  • Fine-grained clock gating sounds like a feature you'd find on an antique timepiece. Actually, it's a feature that Intel has exploited since the design of the Pentium 4. It enables segments of a processor to be told to go to sleep, essentially, by turning off their clock signals. If a component doesn't "hear" a clock tick, it concludes it has nothing to do. To be able to control power consumption at a granular level, addressing as small a segment as possible, engineers fine-grain the CPU's clock gating. The danger with this approach has historically been with power leakage - the more clocks you can switch off, the more opportunities there are for current drain.
  • Dynamic sleep transistors and body-bias techniques are Intel's approach to compensating for this very danger. With dynamic sleep, transistors that don't receive their clock signals can be turned off when in sleep mode, eliminating the possibility for current leakage there. Body biasing then enables the threshold voltage for those sleeping transistors to be lowered, so it doesn't take as much power to switch them back on again.

Intel's goal is to demonstrate turning over a teraflop of performance (or "TFLOPS") - one trillion calculations per second - in a component that utilizes a mere 62 watt power envelope. This isn't so Intel can immediately begin mass producing supercomputers, but instead so the company can start planning its next quantum leap - the next big change in Intel architecture, comparable to its shift away from NetBurst and toward Core Microarchitecture last year.

In a recent interview with BetaNews, In-Stat principal analyst Jim McGregor explained the historical, evolutionary strategies between Intel and AMD:

"Intel is kind of brute-force, where they put a single process in place and multiply it by multiple fabs, [to] make sure the products run on a single process. AMD, and a lot of the rest of the industry, [takes the approach], 'Let's continue tweaking the process around the product.' So where Intel does these major node transitions, AMD and IBM do these sub-node transitions. Within a process generation, they may change things like even the transistor design several times before they go to the next node...So the jumps from process node to process node are bigger for Intel than they are for a lot of the other industry players."

Intel has foregone its usual spring Intel Developer's Forum for the first half of this year, which may be why the company is showing off its Core Microarchitecture developments, along with its 80-core concept CPU, at ISSCC this year instead.

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