How IBM could lead AMD to 32 nm
At this morning's analyst conference, AMD executives said they may scale back some on R&D. But earlier in the week, partner IBM unveiled a plan that could help fill the gap: a way to rework existing 45 nm parts designs for 32 nm.
Early this year, America's two leading semiconductor design firms, in fierce competition with one another to discover a material that could make smaller transistors possible, announced their accomplishments within mere hours of one another: Intel first, followed right behind by IBM.
However, observers at the time noted Intel had already performed very thorough testing on its high-k-plus-metal-gate (HK+MG) process, having already produced a working logic chip at the 45 nm level. IBM could only claim it had found the hafnium material, but beyond some scientific discourses could say little more that was actually practical.
Feeling a little like Al Gore -- beaten by a nose but perhaps not really beaten -- IBM has been working to find some way to leap-frog over Intel's achievement. On Monday, it made some inroads toward that goal, announcing it was forging an alliance with a multitude of semiconductor partners including Samsung, Chartered Semiconductor, STMicroelectronics, Freescale Semiconductor (the holders of Motorola's former CPU-related IP), Infineon (which is still part-owner of US-based Qimonda), and AMD.
Together, that alliance will work to produce HK+MG semiconductors for both logic and memory -- especially for the SRAM needed for CPUs' L1 and L2 caches -- this time at the 32 nm level. It is at this level of lithography that traditional semiconductor materials literally bend under pressure; any smaller, and they will crack. These new chips' die sizes could end up 50% smaller than for similar HK+MG designs at the 45 nm level.
Dr. Gary Patton, vice president for silicon research and development at IBM, explained the meaning of this breakthrough: In the lithographic process, you create semiconductors one layer at a time, as though you were reversing a film of a chip being shaven into layers. Because conventional gate oxide materials leak at lower and lower lithography nodes -- and leakage generates heat -- the HK+MG process replaces that material with something using hafnium, the exact formula of which remaining a secret.
"If you were to look at a picture of a high-k/metal gate device, it would look remarkably similar to a conventional polyoxynitride device," Dr. Patton told BetaNews, officially introducing this publication to the word "polyoxynitride." "Only if you zoom in on that interface would you notice a difference. So it's processed in exactly the same way, with the exception that the gate oxide is replaced by these high-k dielectric and metal gate layers, and then the rest of the process is very similar."
It would be easier on the hafnium material to switch the order in which the gate is laid down, for what's called a "gate-last" process. But doing that would mean changing semiconductors' basic designs and retooling factories to match, a process which Dr. Patton says would be costlier in the end.
"In the gate-last approach, because of the unique features you're trying to achieve...you can imagine you've got some polishing and CMP [chemical mechanical polishing] processes involved, and that ends up introducing some ground-rule restrictions," he went on. "But it's an easier approach because you put the high-k material very late in the process, so it doesn't put as much stress on the high-k material.
"So if you're trying to find the easiest approach to get high-k in, it's with a gate-last approach," the IBM lead engineer continued. "But as a result of some material innovations that we've been able to make, we can put the high-k gate material down in place of the gate oxide, and it can go through the thermal cycles and still have the right properties that we need in terms of interface property and threshold or turn-on voltages."
Because the order of layers doesn't change -- what was gate-first before at 65 nm stays gate-first at 45 nm and 32 nm -- the manufacturing process becomes something in itself that IBM can license to its partners, including SRAM producers STMicroelectronics and Samsung, and CPU manufacturer AMD, Dr. Patton said.
Earlier in the year, the head of IBM's T. J. Watson Research Center, Mukesh Khare, told us that the HK+MG manufacturing process would be critical to the 32 nm process, and absolutely essential to any lithography nodes beyond that. But how soon will all semiconductor manufacturing move to high-k? BetaNews asked Dr. Patton.
"I expect, before we get to the end of 32 nm manufacturing, pretty much all the volume at 32 would be at high-k/metal-gate, because it is such a compelling advantage -- not just the power and the performance but the SRAM. In the SRAM, because of the change from gate oxide to high-k, you get a very significant reduction in gate leakage...At 22 [nm], there is no choice. At 32, I think one can employ very complicated processes such as triple-gate oxide processes, where you put a thinner gate oxide in the logic and a much thicker gate oxide in the array. That's a more expensive process; it will not be as high-performance and low-power as if you went with a high-k/metal-gate process. I think high-k/metal gate is really the preferred way to go at 32 nm."
It was a clever response -- notice Dr. Patton's milestones are grounded at lithography levels, not timelines. So partners such as AMD will not be compelled to march forward into ever smaller realms at a pace set by someone else. Nevertheless, while Intel proceeds on what it calls its "tick-tock cadence" -- for lack of any more appropriate or poetic metaphor -- the tick-tock for AMD is getting much fainter, and it could be because it's IBM that is, very much on purpose, turning down its volume.