AMD Chasing Intel to 45nm by 2008

In an announcement before semiconductor engineers in San Francisco this morning, AMD and IBM put forth proof of what could be their breakthrough process - their response to Intel in the race to reduction. It could pull AMD back even with Intel by 2008, if Intel doesn't respond in the intervening months.

In terms of semiconductor production process advancements, Intel's catapult to 65nm, culminating in last July's release of the first Core 2 Duo processors, put competitor AMD years behind, after it had enjoyed a comfortable lead for many months. For AMD to remain competitive, analysts believe it needs to catch up within no more than two product cycles.

But with Intel having already promised to dispense with 65nm altogether by mid-2008 -- about two product cycles away -- some were starting to get skeptical whether AMD would remain a competitor.


This morning, however, in conjunction with long-time manufacturing partner IBM, AMD gave engineers in San Francisco a first peek into the gauntlet it plans to throw. It's gambling on a new proprietary production process developed at IBM, with the help of AMD, the STI coalition responsible for the Cell processor in Sony's PlayStation 3, and Chartered Semiconductor. If it works, it could be AMD's "leg up" in crossing a significant physical hurdle that has stymied engineers in the race to the next generation of smaller processors.

What's so important about smaller size, beyond increasing yields per wafer? Smaller CPUs, as a matter of physical principle, will consume less power. They actually have to, or they won't work; electric charge has to be minimized in order to eliminate noise. Lower power leads almost directly to gains in efficiency as well, theoretically reducing the amount of leakage to negligible levels.

But to get there, the chemistry has to work out; and up to this point, chemistry has been the problem. The design of semiconductors is all about channeling electric current - getting electrons to go where you want them to go. Accomplishing this on a sub-micron scale means using insulator materials to tease electrons, literally, into following the prescribed direction.

Semiconductor lithography is the process of applying materials atop one another in layers, whose product will be an electronic mechanism. Imagine if you were building a marble run by only applying multiple coats of paint atop one another to create the fences and gates. With semiconductors, the materials you use for the layering help channel those electron "marbles" where you want them to go by way of leveraging their insulating characteristics, or what's called their dielectric properties. A better insulator -- one that's more resistant to current -- makes for a better fence in that it can corral electrons into proper channels. Such a material is said to have a high-k dielectric.

Three years ago, Intel announced its breakthrough in the development of high-k dielectric materials, which enabled it to shrink the size of its silicon dioxide (SiO2) gates below five atomic layers of thickness. Up to that time, SiO2 materials could not be made any thinner without leading to current loss, which is felt as heat. This process, which involved a doping of the SiO2 compound, was also necessary to enable it to mix with the copper of neighboring transistors; unless they could be made chemically compatible, the semiconductor could literally decompose.

This breakthrough enabled Intel to proceed to 65nm lithography, and aim for 45nm by 2007, according to its current roadmap. But semiconductor engineering analysts are saying the doping process might not work at 45nm, specifically in the combination with metal gates. The same advanced film compounds that perform well for Intel at 65nm could break down at 45nm, as the film removal process at that size may create gaps just wide enough to re-introduce the very leakage problem the new compounds were designed to eliminate.

This afternoon, Intel spokesperson Kari Aakre confirmed to BetaNews, "Whether or not we will use high-k at 45nm has not yet been disclosed. All we've said to date is that it's an option we're considering for the 45nm node."

Next: A narrowing window of "low-k" opportunity for AMD

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